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314 from 13 Dec 2020 to 24 Oct 2026
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2026 39

  1. “Performance” Oryon: Qualcomm’s Little Core
  2. Nvidia Vera’s System Architecture: Pushing Bandwidth
  3. NVIDIA’s Olympus Core: Pushing Server Single Threaded Performance Boundaries
  4. Qualcomm’s System Level Architecture in the Snapdragon X2 Elite
  5. Qualcomm’s Adreno X2 GPU
  6. On Binary Translation and its Consequences
  7. Arm’s C2-Ultra, G2-Ultra NX, and CSS N4 IP
  8. Hot Chips 2026: Interviewing IBM's Christian Zoellin & Christian Jacobi
  9. Hot Chips 2026: XCENA and Samsung’s Near-Memory Compute CXL Device
  10. Hot Chips 2026: Samsung’s Processing-in-Memory (PIM)
  11. Hot Chips 2026: Intel’s Crescent Island
  12. Hot Chips 2026: Fujitsu’s Monaka CPU
  13. Hot Chips 2026: Intel’s Diamond Rapids
  14. SiFive’s First Server Platform
  15. Hot Chips 2026: Intel’s Wildcat Lake
  16. Hot Chips 2026: CUDA Targets RISC-V
  17. Hot Chips 2026: Applying High Bandwidth Flash (HBF)
  18. Hot Chips 2026: Samsung and HBM Base Die Opportunities
  19. Talking with Synopsys about the Physics of Chip Design at DAC 2026
  20. NVIDIA’s Vera Whitepaper Has a Thread Loose
  21. Arm’s Cortex A55
  22. RosaicLabs, Atom RTL, and 32-Tile AMX: Trying to Piece Together a x86 Puzzle
  23. AMD Advancing AI 2026: Talking CDNA5 with AMD’s Alan Smith
  24. AMD’s Instinct MI455X: Aiming for the Sun
  25. LLVM Divination of GFX1251’s Differences
  26. Scrying the AMD GFX1250 LLVM Tea Leaves
  27. Is x86 ready to ACE it?
  28. TOP500 at ISC’26: We have a New Number 1
  29. An Interview with Intel's Kira Boyko: Xeon 6+'s Product Director
  30. Evaluating SPEC CPU2026
  31. Evaluating Geekbench 6
  32. Investigating Split Locks on x86-64
  33. Embracing AI with Claude's C Compiler
  34. Microbenchmarking Chipsets for Giggles
  35. Analyzing Nvidia GB10's GPU
  36. Arm's Cortex X925: Reaching Desktop Performance
  37. Arm’s Cortex A725 ft. Dell’s Pro Max with GB10
  38. CES 2026: Taking the Lids off AMD's Venice and MI400 SoCs
  39. Diving into Qualcomm's Upcoming Adreno X2 GPU with Eric Demers

2025 63

  1. Inside Nvidia GB10’s Memory Subsystem, from the CPU Side
  2. SC25: The Present and Future of HPC Networking with Cornelis Networks CEO Lisa Spelman
  3. Nvidia’s B200: Keeping the CUDA Juggernaut Rolling ft. Verda (formerly DataCrunch)
  4. SC25: Estimating AMD’s Upcoming MI430X’s FP64 and the Discovery Supercomputer
  5. Evaluating Uniform Memory Access Mode on AMD's Turin ft. Verda (formerly DataCrunch.io)
  6. SC25: HACCing over 500 Petaflops on Frontier
  7. Qualcomm’s Snapdragon X2 Elite
  8. Strix Halo’s Memory Subsystem: Tackling iGPU Challenges
  9. Evaluating the Infinity Cache in AMD Strix Halo
  10. AMD’s Chiplet APU: An Overview of Strix Halo
  11. Panther Lake’s Reveal at ITT 2025
  12. Interviewing Intel's Chief Architect of x86 Cores at Intel Tech Tour 2025
  13. AMD’s EPYC 9355P: Inside a 32 Core Zen 5 Server Chip
  14. A Look into Intel Xeon 6’s Memory Subsystem
  15. AMD's Inaugural Tech Day ft. ROCm 7, Modular, and AMD Lab Tour
  16. Everactive’s Self-Powered SoC at Hot Chips 2025
  17. AMD’s RDNA4 GPU Architecture at Hot Chips 2025
  18. Intel’s E2200 “Mount Morgan” IPU at Hot Chips 2025
  19. Hot Chips 2025: Session 1 - CPUs
  20. PEZY-SC4s at Hot Chips 2025
  21. Liquid Cooling Exhibits at Hot Chips 2025
  22. Condor’s Cuzco RISC-V Core at Hot Chips 2025
  23. Intel's Clearwater Forest E-Core Server Chip at Hot Chips 2025
  24. Google's Liquid Cooling at Hot Chips 2025
  25. Skymont in Gaming Workloads
  26. Running Gaming Workloads through AMD’s Zen 5
  27. Huawei's Kunpeng 920 and TaiShan v110 CPU Architecture
  28. AMD’s Magny Cours and HyperTransport Interconnect: A High Core Count Blast from the Past
  29. Intel’s Lion Cove P-Core and Gaming Workloads
  30. Blackwell: Nvidia’s Massive GPU
  31. AMD's Freshly-baked MI350: An Interview with the Chief Architect
  32. AMD’s CDNA 4 Architecture Announcement
  33. AMD’s Pre-Zen Interconnect: Testing Trinity’s Northbridge
  34. Qualcomm's Centriq 2400 and the Falkor Architecture
  35. Computex 2025: RX 9060 XT, Threadripper 9000, ROCm, and more
  36. Computex 2025: Nvidia's Keynote
  37. Computex 2025: Intel ARC Pro B-Series
  38. Arm’s Bifrost Architecture and the Mali-G52
  39. Zhaoxin’s KX-7000
  40. RDNA 4’s Raytracing Improvements
  41. Dynamic Register Allocation on AMD's RDNA 4 GPU Architecture
  42. Inside Nvidia's GeForce 6000 Series
  43. An Interview with Oxide's Bryan Cantrill
  44. RDNA 4's "Out-of-Order" Memory Accesses
  45. Looking Ahead at Intel’s Xe3 GPU Architecture
  46. Raytracing on Intel’s Arc B580
  47. AMD's RDNA4 Architecture (Video)
  48. Zen 5's AVX-512 Frequency Behavior
  49. Intel’s Battlemage Architecture
  50. Alibaba/T-HEAD's Xuantie C910
  51. A RISC-V Progress Check: Benchmarking P550 and C910
  52. Inside SiFive’s P550 Microarchitecture
  53. Disabling Zen 5’s Op Cache and Exploring its Clustered Decoder
  54. Sizing up MI300A’s GPU
  55. Inside the AMD Instinct MI300A's Giant Memory Subsystem
  56. Nvidia's Announcements at CES 2025
  57. AMD's Strix Halo - Under the Hood
  58. AMD's CES 2025 Keynote
  59. Intel's CES 2025 Keynote
  60. Digging into Driver Overhead on Intel's B580
  61. Analyzing Lion Cove's Memory Subsystem in Arrow Lake
  62. NeuReality: A Server on a PCIe Card
  63. d-Matrix Corsair: 256GB of LPDDR for AI Models

2024 80

  1. IBM Power - What's Next?
  2. Skymont in Desktop Form: Atom Unleashed
  3. Rebellions: From High Frequency Trading to AI Acceleration
  4. Fujitsu's Monaka CPU: ARMv9, SVE2, and 3D Stacking
  5. Turning off Zen 4's Op Cache for Curiosity and Giggles
  6. 400G Omnipath is Coming: Cornelis Networks at SC24
  7. Examining Intel's Arrow Lake, at the System Level
  8. An EPYC Exclusive for Azure: AMD's MI300C
  9. AMD Disables Zen 4's Loop Buffer
  10. NextSilicon: Putting HPC First
  11. Ayar Labs at Supercomputing 2024: Making Light Move Bits (YouTube Short)
  12. Pushing AMD’s Infinity Fabric to its Limits
  13. Supercomputing 2024: El Capitan, MI300A, and More on the Fastest Supercomputers!
  14. Chips and Cheese's Microbenchmark Framework
  15. AMD's 9800X3D: 2nd Generation V-Cache
  16. Broadwell’s eDRAM: VCache before VCache was Cool
  17. Stability, The Cost Of Intel's Time To Market Approach (Video)
  18. Running SPEC CPU2017 on Chinese CPUs, and More
  19. AMD's Turin: 5th Gen EPYC Launched
  20. Lunar Lake’s iGPU: Debut of Intel’s Xe2 Architecture
  21. The Next Stage for Chips and Cheese
  22. Skymont: Intel’s E-Cores reach for the Sky
  23. Chips and Cheese Interviews Ronak Singhal
  24. Lion Cove: Intel’s P-Core Roars
  25. Intel Granite Rapids: A Step in the Right Direction (Video)
  26. Intel’s Redwood Cove: Baby Steps are Still Steps
  27. Running SPEC CPU2017 at Chips and Cheese?
  28. Discussing AMD’s Zen 5 at Hot Chips 2024
  29. FuriosaAI’s RNGD at Hot Chips 2024: Accelerating AI with a More Flexible Primitive
  30. Telum II at Hot Chips 2024: Mainframe with a Unique Caching Strategy
  31. An Interview with Susan Eickhoff and Christian Jacobi from IBM at Hot Chips 2024
  32. An Interview with Intel’s Arik Gihon about Lunar Lake at Hot Chips 2024
  33. AmpereOne at Hot Chips 2024: Maximizing Density
  34. Tesla’s TTPoE at Hot Chips 2024: Replacing TCP for Low Latency Applications
  35. Hot Chips 2024: Qualcomm’s Oryon Core
  36. AMD’s Radeon 890M: Strix Point’s Bigger iGPU
  37. Zen 5 Variants and More, Clock for Clock
  38. AMD’s Ryzen 9950X: Zen 5 on Desktop
  39. AMD’s Strix Point: Zen 5 Hits Mobile
  40. Cortex A73’s Not-So-Infinite Reordering Capacity
  41. Grace Hopper, Nvidia’s Halfway APU
  42. Zen 5’s 2-Ahead Branch Predictor Unit: How a 30 Year Old Idea Allows for New Tricks
  43. Arm’s Neoverse V2, in AWS’s Graviton 4
  44. Arm’s Cortex A73: Resource Limits, What are Those?
  45. A Video Interview with Mike Clark, Chief Architect of Zen at AMD
  46. Qualcomm’s Oryon Core: A Long Time in the Making
  47. The Snapdragon X Elite’s Adreno iGPU
  48. Examining the Nintendo Switch (Tegra X1) Video Engine
  49. Testing AMD’s Giant MI300X
  50. Testing AMD’s Bergamo: Zen 4c Spam
  51. Intel Details Skymont
  52. Tracing Intel’s Atom Journey: Goldmont Plus
  53. Intel’s Lion Cove Architecture Preview
  54. Thoughts on Skymont Slides
  55. Update on Meteor Lake DRAM Latency Measurements
  56. Comparing Crestmonts: No L3 Hurts
  57. Qualcomm’s Oryon LLVM Patches
  58. Meteor Lake’s E-Cores: Crestmont Makes Incremental Progress
  59. Chips and Cheese State of the Union
  60. Correction on Qualcomm iGPUs
  61. Inside the Snapdragon 855’s iGPU
  62. Can China’s Loongson Catch Western Designs? Probably Not.
  63. Sizing up Qualcomm’s 8cx Gen 3 iGPU
  64. Intel Meteor Lake’s NPU
  65. Raytracing on Meteor Lake’s iGPU
  66. Intel’s Ambitious Meteor Lake iGPU
  67. Inside Control Data Corporation’s CDC 6600
  68. Why x86 Doesn’t Need to Die
  69. The Nerfed FPU in PS5’s Zen 2 Cores
  70. Loongson 3A6000: A Star among Chinese CPUs
  71. Inside Snapdragon 8+ Gen 1’s iGPU: Adreno Gets Big
  72. Ryzen Z1’s Tiny iGPU
  73. LLVM’s Ampere1B Commit
  74. AMD’s Mild Hybrid Strategy: Ryzen Z1 in ASUS’s ROG Ally
  75. AMD RDNA 3.5’s LLVM Changes
  76. Examining AMD’s RDNA 4 Changes in LLVM
  77. Inside Qualcomm’s Adreno 530, a Small Mobile iGPU
  78. Previewing Meteor Lake at CES
  79. Maxwell: Nvidia’s Silver 28nm Hammer
  80. A New Year and New Tests: GPU L1 Cache Bandwidth

2023 58

  1. Nintendo Switch’s iGPU: Maxwell Nerfed Edition
  2. AMD’s CDNA 3 Compute Architecture
  3. Cortex A57, Nintendo Switch’s CPU
  4. GCN, AMD’s GPU Architecture Modernization
  5. Inside Kepler, Nvidia’s Strong Start on 28 nm
  6. China’s New(ish) SW26010-Pro Supercomputer at SC23
  7. Coming soon
  8. ARM’s Cortex A72: aarch64 for the Masses
  9. Core to Core Latency Data on Large Systems
  10. CPU-Z’s Inadequate Benchmark
  11. A Brief Look at Apple’s M2 Pro iGPU
  12. Cortex X2: Arm Aims High
  13. Cinebench 2024: Reviewing the Benchmark
  14. Arm Announces Total Design: Taking Neoverse CSS Forward
  15. Starfield on the RX 6900 XT, RX 7600, and RTX 2060 Mobile
  16. AVX10/128 is a silly idea and should be completely removed from the specification
  17. Zen 5’s Leaked Slides
  18. Qualcomm’s Hexagon DSP, and now, NPU
  19. Arm’s Cortex A510: Two Kids in a Trench Coat
  20. Intel’s Ponte Vecchio: Chiplets Gone Crazy
  21. Hot Chips 2023: AMD’s Phoenix SoC
  22. Analyzing Starfield’s Performance on Nvidia’s 4090 and AMD’s 7900 XTX
  23. Arm at HC35 (2023): CSS-Genesis
  24. Hot Chips 2023: Arm’s Neoverse V2
  25. Hot Chips 2023: Characterizing Gaming Workloads on Zen 4
  26. Hot Chips 2023: SiFive’s P870 Takes RISC-V Further
  27. Hot Chips 2023: Ventana’s Unconventional Veyron V1
  28. Ivy Bridge’s Gen7 Graphics: Intel’s Modern iGPU Push
  29. Correction for A710/Neoverse N2’s FP Scheduler Layout
  30. ARM’s Neoverse N2: Cortex A710 for Servers
  31. ARM’s Cortex A710: Winning by Default
  32. Sandy Bridge: Setting Intel’s Modern Foundation
  33. AMD’s Radeon Instinct MI210: GCN Lives On
  34. Genoa-X: Server V-Cache Round 2
  35. Kryo: Qualcomm’s Last In-House Mobile Core
  36. Nvidia’s H100: Funny L2, and Tons of Bandwidth
  37. AMD’s EPYC 7J13: Zen 3 Customized
  38. Latency Testing is Hard (RDNA 3 Power Saving)
  39. AMD’s RX 7600: Small RDNA 3 Appears
  40. ARM’s Cortex A53: Tiny But Important
  41. Shader Execution Reordering: Nvidia Tackles Divergence
  42. Cyberpunk 2077’s Path Tracing Update
  43. AMD’s 7950X3D: Zen 4 Gets VCache
  44. Codecs for the 4K Era: HEVC, AV1, VVC and Beyond
  45. Loongson’s 3A5000: China’s Best Shot?
  46. AMD’s HD 6950 vs RX 6900 XT: What Does Adding 50 Do?
  47. Raytracing on AMD’s RDNA 2/3, and Nvidia’s Turing and Pascal
  48. Sapphire Rapids: Golden Cove Hits Servers
  49. Van Gogh, AMD’s Steam Deck APU
  50. Loongson’s LSX and LASX Vector Extensions
  51. AMD’s RDNA 2: Shooting For the Top
  52. Intel’s Dunnington: Core 2 Goes Dun Dun Dun
  53. Previewing China’s Loongson 3A5000 with Performance Counters
  54. Bulldozer, AMD’s Crash Modernization: Caching and Conclusion
  55. Bulldozer, AMD’s Crash Modernization: Frontend and Execution Engine
  56. Golden Cove’s Vector Register File: Checking with Official (SPR) Data
  57. Microbenchmarking AMD’s RDNA 3 Graphics Architecture
  58. AMD’s Zen 4, Part 3: System Level Stuff, and iGPU

2022 40

  1. Golden Cove’s Lopsided Vector Register File
  2. Was Rocket Lake Power Efficient?
  3. Knight’s Landing: Atom with AVX-512
  4. Cannon Lake: Intel’s Forgotten Generation
  5. AMD’s Zen 4, Part 2: Memory Subsystem and Conclusion
  6. AMD’s Zen 4 Part 1: Frontend and Execution Engine
  7. Microbenchmarking Nvidia’s RTX 4090
  8. Why you can’t trust CPUID
  9. Addendum: Clock Ramp on ADL, Zen 4, M1, and More
  10. Microbenchmarking Intel’s Arc A770
  11. Skylake: Intel’s Longest Serving Architecture
  12. Hot Chips 34 – Biren’s BR100: A Machine Learning GPU from China
  13. China’s Phytium D2000: Building on A72?
  14. Nvidia’s RTX 4090 Launch: A Strong Ray-Tracing Focus
  15. Hot Chips 34 – AMD’s Instinct MI200 Architecture
  16. How Quickly do CPUs Change Clock Speeds?
  17. Hot Chips 34 – Intel’s Meteor Lake Chiplets, Compared to AMD’s
  18. Hot Chips 34 – Tesla’s Dojo Microarchitecture
  19. Tachyum’s Revised Prodigy Architecture
  20. A Preview of Raptor Lake’s Improved L2 Caches
  21. AMD’s Athlon 64: Getting the Basics Right
  22. Caching Energy Efficiency Data – Mobile and AVX-512
  23. Alder Lake’s Caching and Power Efficiency
  24. Tachyum: Too Good to be True?
  25. Intel’s Netburst: Failure is a Foundation for Success
  26. Sunny Cove: Intel’s Lost Generation
  27. Graviton 3: First Impressions
  28. iGPU Cache Setups Compared, Including M1
  29. Examining Centaur CHA’s Die and Implementation Goals
  30. Centaur CHA’s Probably Unfinished Dual Socket Implementation
  31. Intel Renames Oregon Fab: Gordon Moore Park. Adds +270k sq ft, 18A Node now 2024
  32. GPU Hardware Video Encoders – How Good Are They?
  33. VIA Part 4 – A Deep Dive into Centaur’s Last CPU Core: CNS
  34. SiFive Completes Series F Funding Round: +$175m, $2.5b Evaluation
  35. State of Windows on Arm64: a high-level perspective
  36. Going Armchair Quarterback on Golden Cove’s Caches
  37. Alder Lake’s Power Efficiency – A Complicated Picture
  38. Deep Diving Zen 3 V-Cache
  39. AMD’s V-Cache Tested: The Latency Teaser
  40. Intel’s Tremont: Atom Changes Course

2021 31

  1. Gracemont: Revenge of the Atom Cores
  2. Alder Lake – E-Cores, Ring Clock, and Hybrid Teething Troubles
  3. Popping the Hood on Golden Cove
  4. Zhaoxin Part 3: A Sort of Anti-Climax
  5. Deep Diving Neoverse N1
  6. Do IBM’s Giant L3 and V-Cache Represent the Future?
  7. The Weird and Wacky World of VIA Part 2: Zhaoxin’s not quite Electric Boogaloo
  8. Analyzing Video Card Efficiency, Part I – Power
  9. The Weird and Wacky World of VIA, the 3rd player in the “Modern” x86 market
  10. Details on the Gigabyte Leak
  11. Neoverse N1 vs Zen 2: ARM in Practice
  12. Measuring Zen 3’s Bottlenecks
  13. ARM or x86? ISA Doesn’t Matter
  14. How Zen 2’s Op Cache Affects Performance
  15. The End of an Era: AMD Discontinues Pre-2016 GCN GPU Support
  16. Nvidia’s Ampere & Process Technology: Sunk by Samsung?
  17. Exploring CPU Core to Core Latency and the Role that Locks Play
  18. GPU Memory Latency’s Impact, and Updated Test
  19. RDNA 1 Redux: Maximizing Performance With RX 5000 Series GPUs
  20. Measuring GPU Memory Latency
  21. Rocket Lake: When ‘Reviews’ are Really Previews
  22. Lowering the BAR: AMD’s 6700 XT launch and the Importance of Disclosure
  23. Modern Data Compression in 2021 Part 2 : The Battle to Dethrone JPEG with JPEG-XL, AVIF, and WEBP
  24. Analyzing Zen 2’s Cinebench R15 Lead
  25. CTR Safety, Revisited
  26. Security and You, an Overview
  27. AMD’s Past and Future CPUs (Formal Retraction)
  28. CTR: A Review and a Warning (updated)
  29. Modern Data Compression in 2021 Part 1: A Simple Overview on the Art of Image Encoding
  30. Intel Finally Solving the Right Problem
  31. Intel’s HEDT Roadmap

2020 3

  1. NVIDIA’s Next Generation GPU: MCM?
  2. NVIDIA’s Enterprise
  3. Welcome to Chips and Cheese