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166 from 1 Mar 2020 to 25 Oct 2026
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2026 21

  1. Using the AXI DMA on Versal with the pyxdma driver
  2. Building a Nios V soft processor system on the Agilex 3 dev kit
  3. Including Local AI in FPGA Development Workflow
  4. Reconfiguring the Agilex 3 FPGA fabric from Linux without rebooting
  5. Running Linux on the Agilex 3 HPS and adding a custom IP to the fabric
  6. The Gate Array News 2026.
  7. Red Pitaya STEMlab MCP: Giving an AI Agent Control of the Verification Bench
  8. Getting Started with the Forgix Board: Efinix Trion T8 + RP2354
  9. Using the Red Pitaya STEMlab 125-14 PRO Gen 2 as an SDR in GNU Radio
  10. Implementing a Single-Precision Floating-Point Biquad on Versal
  11. CryptoliteICE: an Open-Source FPGA-Based TRNG
  12. Building PetaLinux for a Versal-Based Board This week I have been busy working on my talk in the next FPGA Developer’s Forum, which will be focused on the AMD Versal architecture and the iWave Global iG-G57D. As part of the preparation, I needed to build a PetaLinux image for the board, which is a c
  13. Exploring Versal ACAP with the iG-G57D Board I have been using Zynq7000 and Zynq MPSOC devices for years, but I had not had the chance to work with AMD’s latest adaptive platform, Versal ACAP, until now. A few weeks ago, the iWave Global iG-G57D board, based on the Versal AI Edge VE2302, landed into
  14. Getting started with Agilex 3 and floating-point DSP operations I have been working with Xilinx (now AMD) FPGAs for years, so when the Agilex 3 FPGA and SoC C-Series Development Kit landed on my desk I knew the transition would involve some hard changes. I used Quartus in my University days with a T
  15. Remote FPGA verification of DSP algorithm using STEMlab 125-14 PRO Gen 2 When I was in the university. I remember my FPGA professor saying how important is to simulate our designs. To be honest, in that moment simulations were something boring and I just wanted to get an FPGA development board and t
  16. Red Pitaya STEMlab 125-14 PRO Gen 2: Analysis of an audio signal modulated using PWM I know Red Pitaya almost since its Kickstarter campaign, and I have been using it for a while now. It is one of those boards that you can bring always with you, actually I have an old one and it came always in my ba
  17. Implementing AES-128 in Verilog: ECB core and CTR wrapper Usually when we hear about cryptography we think about Bitcoin, NSA and NVIDIA GPUs, but cryptography is much more than that, and it is a key part of our cybersecurity. Unlike digital signal processing algorithms or control systems, cryptogra
  18. Why hardware models can beat software mocks: SPI INA239 and robot arm models This week I gave a talk in a SW quality meetup. The talk was focused on a practical idea: when we develop software that must communicate with hardware, a hardware model implemented in FPGA can be more useful than a simple s
  19. Internal USB header JTAG cable with an FT232H I am a great fan of buying cheap FPGA accelerator cards and repurposing them for experiments and custom workloads. Now, I have a computer where I test this boards and use it as a development platform for various projects. However, I always need to have a
  20. AS02MC04 (Alibaba Cloud) Kintex UltraScale+ NIC I am not sure if it was Santa Claus or the Three Wise Men (SSMM Los Reyes Magos) who brought it to me, but I finally have one of these interesting little FPGA NIC cards to play with: the AS02MC04 from Alibaba Cloud. This board is built around an AMD/Xi
  21. Enable an AI chat on MicroBlaze with the Arty A7-35T A new year has arrived, and I want to start the season with a project that leaves no one indifferent. Since 2025 is the year of AI and AI agents, it has to be an AI project. I also wanted something different: not AI code generation or testbenches,

2025 24

  1. Enabling Custom PL Overlays & Generic-UIO on Kria KR260 with PetaLinux 2025.1 The Kria SOM board were a game-changer in the FPGA/SOC ecosystem. That a SOC manufacturer decided not only to sell the SOC, but also the SOM that includes it, and a full development kit, was a bold move that paid off. The
  2. KR260 video capture with Jupyter + Python (libGL Mesa) Video is probably the most hyped field in which FPGAs are used, at least until the AI arrival. I have to say that I worked with video very few times, and those times were from the FPGA side reciving video data from MIPI interfaces and send it to
  3. AI-assisted testbench Generation for FPGA Designs I use AI every day, especially for documenting and learning. Last week I was testing an SPI slave and wondered how a testbench generated by AI would work. A few options came to mind: would a black-box test be better? A gray-box test? What about givin
  4. Receiving ADS-B (1090 MHz) with a USRP B206mini-i and GNU Radio Disclaimer: This article is provided for educational and research purposes only. Any signal capture, analysis, or related activity should be performed exclusively in a controlled lab environment and in full compliance with applicable la
  5. Using the PolarFire SoC Cryptographic Processor FPGAs and SoCs are becoming essential assets in our daily lives. From AI to real-time systems, they power many of today’s technological advances. As a result, they store sensitive data and can be targets for third-party attacks, but they are also built
  6. MicroBlaze-V on Spartan UltraScale+. The Spartan UltraScale+ platform is currently AMD’s darling. At the FPGA events I attended this summer, the SCU35 had a special place — especially at the recent FPGA Horizons, where this board could be found not only at the AMD booth but also at AVNET’s booth.
  7. Getting Started with the SCU35 and Spartan Ultrascale+ Spartan UltraScale+ has been officially released, and AMD has provided a development board to help engineers get familiar with this device. The board is called the SCU35.
  8. FPGA Security Features: Protecting Your Bitstreams and Designs Again, we are under attack, and our FPGA designs are not an exception. When someone talks about hostile environments, usually we think of wars, a nuclear reactor, or Jupiter; however, a hostile environment is everywhere outside our offic
  9. Sending PL overlays from Ubuntu in the KR260 PetaLinux is probably the go-to OS when working with Zynq devices. It makes life easy because it is built for these chips and comes with plenty of pre-configured Yocto layers that take care of most of the setup for you. But here is the catch: AMD itself h
  10. The Gate Array News 2025. It’s July again, and a new season is coming to an end. During this period, we’ve explored a range of topics on the blog: from how to implement electrical models on FPGAs—even on very small ones—to optimizing Speedgoat models using the fixed-point solver.
  11. True random number generators based on FPGA In cybersecurity, random numbers are extremely important, and the security of some cryptographic algorithms depends directly on the quality of the random numbers generated. Typically, random numbers are produced using software algorithms. However, these ar
  12. Parallelizing SHA256 calculation on FPGA A few weeks ago, I wrote an article where I developed a hash calculator on an FPGA. Specifically, I implemented an SHA-256 calculator. This module computes the hash of a string (up to 25 bytes) in 68 clock cycles. The design leverages the parallelism of FPGAs
  13. Streaming data to DDR memory from PL on Arty board. In the last article, we talked about using the AXI Datamover IP, which allows us to perform DDR memory transactions in a way very similar to how we would with an SoC and AXI DMA. The article used the YPCB-00388-1P1 board to transfer data from PCIe
  14. Streaming data to DDR memory from PL. HW design. We are living in a kind of data fever. Today, certain types of data are even more valuable than gold. And just like gold, data must be transported from its origin to the place where it will be used. We can extrapolate this to computing, where data is
  15. Getting started with the Ebay's Kintex7 Accelerator To be honest, this week I had prepared another article about the carrier recovery algorithm. However, I received a board I bought some weeks ago on EBAY, and I was eager to try it out. The board is a PCIe FPGA accelerator based on the AMD Kintex7 X
  16. Writing Verilog code with Copilot I have to admit that I started using AI tools like Copilot and ChatGPT a few months ago. Initially, I was resistant to the idea. However, after testing them on some projects, I was surprised, and now I frequently use them to generate auxiliary scripts. To be honest,
  17. Do you need an FPGA? In my professional career, I have often been asked the question: what is an FPGA? FPGAs are not as well-known as devices like microcontrollers, which is why they are not widely used. However, this presents a great opportunity for FPGA developers. Although FPGAs are not commonly
  18. SHA256 compute in Verilog On my last visit to the Embedded World, one of the most popular topics was Cyber Resilience Act and Cybersecurity, and FPGA had much to say in this area. They are fast, they can execute algorithms in parallel, and they are in the lower level of an ethernet interface checkin
  19. My visit to the Embedded World Conference Last week I was in Nuremberg assisting at the Embedded World Conference. This is not my first time there, I was there also in 2023 but this year was special, it was my first year as a speaker, talking about real-time simulations on FPGA, but I am going to ta
  20. Creating Pyhon driver for the AXI DMA IP If someone asks me about the most useful peripheral of embedded systems, I do not doubt that the DMA (Direct Memory Access) is at my top. This is not just for Zynq devices, but from TI DSP, to Microchip devices, being able to move data from a peripheral, or a
  21. Creating a custom Petalinux image for RedPitaya STEMlab Some time ago, I wrote an article about how to create a custom hardware design for a RedPitaya STEMlab. Although the article was written in September 2023, things have changed a bit around Vivado and Petalinux. Since in that article I focused o
  22. The Open Logic project One of the reasons to writing this blog was to share content and projects about FPGA. When this blog started, in 2020, there were some open-source projects like Yosys or Verilator. Fortunately,the amount of this kind of project, and the number of FPGA engineer that are sharing
  23. Adding custom RTL modules to an electrical model Tools like Matlab and Simulink offer engineers a bunch of packages to do their jobs. As FPGA developers, the packages that, in some cases, could make our designs faster to develop are HDL Coder and HDL Verifier. In addition, if we mix those packages w
  24. The end of the world The Mayas predicted the end of the world in 2012. Engineers said that the year 2000 was going to be critical for many systems based on computers. According to the UNIX time, systems won’t be able to work after January 19th of the year 2038. All of them were wrong, the end of the

2024 25

  1. Using the AXI DMA in Petalinux 2024.1 A year ago I wrote an article about how to use the AXI DMA peripheral within Petalinux. This article worked at the moment I wrote it but a year later, it stopped working. I am not 100% sure of the cause, but I think that it is related to the newest versions of t
  2. Using a fixed-point solver on Speedgoat model. In this blog, you have seen filters, regulators, and other kinds of DSP algorithms implemented in Verilog, and all of them have something in common, all of them were implemented using fixed-point precision. The reason for this is simple, I didn’t need m
  3. Deploying a Buck-Boost model on a custom HIL platform. A few years ago, I found the hardware-in-the-loop (HIL) platform to be very interesting. I am sure that you have noticed this because of all the articles I write about these platforms and modeling. What makes interesting for me these platforms i
  4. Understanding the PID regulator. I always remember when the Optimization and Optimum Control teacher at the university told us that 90% of the regulators we will find in our life, will be PID, 5% will be LQR and the other 5% will be other complex regulators. PID control has become the most used cont
  5. Modeling a Boost converter in Speedgoat Performance. It has been some since the last time we talked about Speedgoat, and during this summer I have been working with it deploying some models. In this blog we saw how to deploy a Buck converter electrical model using Speedgoat, this time we are going t
  6. Deploying a converter model on the Leonidas board When discussing real-time simulations, we often think of big and powerful devices. In the same way, when we talk about Hardware-In-the-Loop (HIL), we think on FPGA like the Kintex7 used in the Speedgoat Performance so, do we need huge FPGAs to perfor
  7. Co-simulating Verilog and SPICE circuits with QSPICE If you are an engineer in any field related to electricity, in your degree I am pretty sure that you have simulated many electronic circuits, from linear circuits based on operational amplifiers to power circuits like switched-mode power supplies
  8. Building Linux with Buildroot for the KD240 Kit If I say Linux and Zynq MPSOC, I am pretty sure that most of you think of Petalinux. Petalinux is the official AMD’s tool that eases the build of a Linux distribution for FPGA and SoCs. What Petalinux gives us is a set of pre-configurations or recipes
  9. Creating a HDL Coder Support Package for Leonidas board When we are working in any engineering field, probes of concept are essential in order to check if an idea can become a real product. The time spent in the probe of concept is crucial either to accept that probe of concept as a future product o
  10. The Gate Array News 2024. Another season comes to an end, and The Gate Array News is here. This is the second edition of this series os articles, and I think that it would be a very interesting exercise to recover the news of the last TGA News. In 2023 we talked about the announcement of Spartan 7 U
  11. Getting started with the MPFS Discovery Kit When the MPFS Discovery Kit was released, I thought that this board was what the Icicle Kit was supposed to be. A small board, with enough interfaces, even a MIPI interface for high-speed communications, Ethernet, SD Card, LEDS, Buttons… and the best, USB
  12. FPGA Conference 2024 This week I have been in Munich for the FPGA Conference Europe. This event is based on a set of conferences separated in six different tracks. In addition, there is a showroom where you can find different booths where they show new products and demos. In this article, I am going
  13. Base acceleration design for Genesys ZU 5EV In this blog we have used many different boards, many from Digilent but also boards from AMD or Trenz. Now, if you search in internet about acceleration using AMD parts, you will find many articles that use the new Kria SOMs, either the KV260, the KR260 or
  14. Using PS clocks for your PL designs Sometimes people who want to start in the FPGA world ask me for a recommendation of a development board to start with. My answer to this question is always a Zynq board for several reasons. First, maybe they are not interested now in using the PS of a Zynq, but if
  15. Undersampling. Playing with Nyquist and Shannon. This week, Digilent released the Zmod SDR, a new ZMOD module with SYZYGY interface intended for SDR projects. The features of this new Zmod include 2 RX channels with 14-bit resolution and an analog bandwidth from just 35 kHz to 470 MHz. The very inte
  16. Creating a custom AXI IP. The professional way. Since you are reading this blog, I am pretty sure that you have used an AMD IP in at least one of your designs. Also, if you wanted a so specific IP for a specific project, likely you have bought an IP from a third-party vendor. Creating an IP, using i
  17. BLDC motor control with the KD240 In the last article, I generated a base project for the KD240 kit from AMD. This kit is based on the Kria K24 SOM, the smallest brother of the K26 SOMs used in the KR260 and KV260. Since this board was released I have been interested in it because, I am not 100% sur
  18. Running Petalinux 2023.2 on the KD240 Every year, AMD releases several versions of all its development environments. From Vibado to Petalinux, all the environments are updated and introduce several changes in the way we use them. In this article, we are going to generate a hardware project with the
  19. Implementing and ADC inside the FPGA In my job, and also in the blog, I used to work with hardware-in-the-loop (HIL) systems. These devices can simulate in real-time the behavior of different analog circuits, and allow us to design algorithms and electronic circuits to control those circuits and tes
  20. Running subcycle average models on Speedgoat Performance System (II). In this post, we talked about the PWM signals, and how we can capture them to convert that discontinuous signal into a continuous signal. This process is called subcycle average. Now, how can we integrate the subcycle average in a
  21. Solving a Boost converter in FPGA A few weeks ago I read an article that talked about how to solve differential equations on FPGA. That article was very interesting but then I realized that it is not a complex task for FPGA as long as the equation could be discretized. The problem comes when you mix
  22. Connecting an FPGA accelerator to the Raspberry Pi 5 Since the first version of Raspberry Pi was released in 2012, four more versions of this Single Board Computer (SBC) were released. The fourth version came with a new feature that increased the power of that SBC. That version was the first with PC
  23. Running subcycle average models on Speedgoat Performance System (I). Materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) are making our power electronics converters faster and faster. This means small inductors and capacitors that make, in most cases, the cost of the devices decrease. This
  24. Getting started with ZuBoard and Petalinux In the last post we talked about the possibilities that working with a Zynq MPSOC device offers us. Also, on LinkedIn, there was a conversation about the new roles that the industry will need to work with complex devices that feature different architectures
  25. The art of sharing Again, you are reading the first post of the year, there are three of these posts for now, and the show will go on. For the first post of 2024, I am going to publish an article that explains a talk that I presented at a conference, but they rejected it, so since I already had some

2023 25

  1. Getting started with the RP2040 PMOD The end of 2023 has been a HW time. I have developed some boards that I will use in 2024 in different projects. One of the last boards of the year is the RP2040 PMOD, a PMOD-compatible board with a Raspberry PI microcontroller, the RP2040. This microcontroller is
  2. Implementing a DC remover filter on FPGA Many digital signal processing systems like audio processors or QAM decoders need at their input an AC signal and just an AC signal. The presence of a DC component, or DC bias in the input signal can make our system saturate or generate some type of missfunct
  3. Using an RP2040 for programming and debugging the CP SOM ONE When we design a board for a programmable device, an important thing that we have to consider is how to program that board. This was the question I asked myself when I designed the CP SOM ONE. In the first version of the SOM, I added a JTA
  4. Data acquisition from an electric model running on the FPGA of a Speedgoat Performance. If there is a device that I would really like to have, it is a hardware-in-the-loop test system. These devices allow you to have almost any hardware circuit on your desktop with, in general, limited space. We alr
  5. Designing an FPGA SOM. In the market we can find many different FPGA boards with infinite interfaces, peripherals, connectors… so anyone can think, why you would need to develop your own FPGA board. You just have to find a development board that meets most of your requirements, especially if you are
  6. Getting started with a Zynq development board. Base PS Design. A sales representative has given you a Zynq development board, it has even a heat sink! It seems powerful. When he/she leaves your office you run to your desk to connect your new board to the USB or the AC adapter. The board is alive, so
  7. Custom HW design for Red Pitaya STEMlab A few weeks ago we talked here about the Red Pitaya STEMlab board. We saw how we can use its web-based environment to deploy different APPS and also how using Python we could read and write analog and digital data to a credit card size board. As I mentioned in
  8. My FPGA development environment When a developer wants to start to develop, the first they have to do is install the development environment. This usually is not a big deal, you just have to download the environment installation file and install it. Maybe, if you use Linux as your operating system,
  9. Getting started with Red Pitaya STEMlab A few years ago, I started to hear about Red Pitaya. The first I heard about this device is that it was a Zynq-based board, actually, a Zynq-based development board. Then, doing some research on the internet I discovered that it is not just a development board
  10. The Gate Array News 2023. Another season is coming to an end. This season in controlpaths.com have been published 24 articles talking about SDR, developing designs for Microship’s PolarFire SoC, implementing designs in the cloud and also a great collaboration with Speedgoat (SPOILER: This will conti
  11. Designing IIR filters in Python. Calculating the coefficients of an IIR filter is something familiar in this blog. In general, when I have to design a new filter, I usually do it in MATLAB because I already have a set of scripts to design different types of filters. Things get complicated when, for
  12. Implementing a Buck converter in RTL. FPGAs are great devices to make math and, fortunately, almost all in this world are maths so, can we implement anything on an FPGA? Uhh I wouldn’t like to say yes fastly but, maybe… In this blog, we saw how we can implement physical models on an FPGA using MATLA
  13. Developing a SYZYGY peripheral A few years ago, when I started to hear about SYZYGY, it seems me very useful interface because it is in the middle of PMOD and FPGA Mezzanine Card (FMC). Before that, all high-speed interfaces, even if they use only a few pins, were connected to the carrier board usin
  14. DMA, Petalinux and the ZUBoard-1CG NOTE: The procedure described in this article has change with the latests Linux Kernels. I am working on a new version of this article. Zynq MPSOC are complex device. Complex because its Processing System (PS) is based on a heterogeneous multi-core consisting of a
  15. Simulating DSP algorithms using Verilog. When you think about DSP algorithms, sure you think of applications such as MATLAB, Octave or Python. In the same way, when you think about simulating HDL, to your head comes words like Verilog or VHDL, but, what happens when we mix these worlds? When we have
  16. Working with Kria SOM. In this blog, we already talk about the kit KR260 in this post. In that post, we used the KR260 to implement an acceleration design. The cost and the power of this development board make it a very interesting board to deploy Zynq MPSOC designs. If we compare its cost, around 3
  17. Capturing the ISM band with RTL SDR. When I started to play with SDR devices, I didn’t realize how many signals can be captured with these devices. We are surrounded by radio signals like WIFI, Bluetooth or 4G. These signals, although we don’t know exactly how they work, we are comfortable with them
  18. Configuring the PL design from the PS on Zynq MPSOC. Since the early 90s, JTAG is the standard to program many different embedded devices like microcontrollers, processors and also FPGA. This standard is based on a serial protocol that allows the connection of different devices in a chain mode. JTAG
  19. Running Ubuntu in the Microchip's Icicle Kit. RISC-V processors are everyday more used in many different applications. This is why companies like Canonical are releasing their Linux distributions for devices based on RISC-V. One of the latest devices added to this family is the Microchip’s Icicle Ki
  20. New blog. If you have arrived here, you will notice that some changes are made in controlpaths.com, but the most important changes are behind. Controlpaths is now based on Jekyll, which allows me to write my posts using Markdown, with all the advantages that this brings to me like code highlight and
  21. Vitis acceleration flow and the KR260. Since a few years ago, FPGA are widely used for acceleration. In this blog, we have talked about how we can connect an FPGA to the PCI socket of our computer, and interchange data between the processor and the FPGA. SOCs, give us the chance to have in a single
  22. Running a physical model on a Speedgoat. I have said in some posts that you can do everything with an FPGA, and although that affirmation is false, an FPGA cannot do an omelet for example, you can indeed do many things with an FPGA. Because of their parallel nature, and speed, FPGA are widely used t
  23. Adding a MicroBlaze coprocessor to an edge computer. In the industry, we can find many different applications, and most of them, especially in recent years, these applications require some kind of computing. Acquiring data on where the application is, and processing the data later in any other locat
  24. Getting started with Speedgoat. On this blog we have seen many projects where we have used FPGA, in general using development boards, unfortunately, there are not many cases where I can show you an FPGA in a real application, but this is one of these cases. The device I am talking about is a Real-Ti
  25. The FPGA invasion Let’s come back 20 years ago. FPGA are mystical devices used in exotic applications. They came from programmable PAL memories that could be used to execute simple logic operations, and not only simple but the amount of logic that they could execute was also very low. These simple d

2022 26

  1. Using the Python API for USRP SDR devices. On my job, I use python almost every day to develop auxiliary scripts for executing tests, automate some CICD flows or control equipment to emulate hardware. I have to say that I am very comfortable with Python because, for my use level, the language is ver
  2. Implementing QAM16 on FPGA. When we talk about SDR, in general, we think of closed devices that are connected to the computer and, using some kind of software, proprietary or open source, can acquire and, most important, decode the radio signals. Sometimes the decoding process is executed in the com
  3. Implementing FPGA designs in the cloud If you are working with FPGA, maybe you use different environments to write your code and implement your design or perform continuous integration (CI/CD). In my case, in my job, I use a Windows PC to write the code and document it, and a remote machine with Lin
  4. Writing Verilog code using Python with Migen. Many people who never have used a Hardware Description Language (HDL), either Verilog or VHDL, thinks that these languages are weird. Actually, being able to generate code that is executed in parallel make the head of software developers explode, yes dev
  5. A different approach to the discrete Fourier transform. The calculation of the Discrete Fourier Transform (DFT), like filtering, are by far the most common digital signal processing algorithms. When I started to investigate about the DFT, I noticed that I needed a large background before understand
  6. Creating a custom PolarFire SoC design. FPGA manufacturers are determined to show us how their devices can do very difficult things like process video, detect in that video who is wearing a mask and who is not, detect if the people is happy or not… all of this while a led is blinking. This make that
  7. Debugging a Microchip's SmartFusion2 SoC. When I started to develop designs for FPGA, the thing that I missed from the digital signal processors is the debug capabilities. I used to debug my programs using JTAG that performs “real time” reads of the data memory, so I was able to see the value of alm
  8. Trying to hack a garage door opener with the USRP B210. National Instruments recently released the USRP B206mini-i, a new portable SDR with a range from 70 MHz to 6 GHz with an USB-C interface compatible with most of the laptops. When we think about radio signals, we often think that all of them are
  9. F4PGA and Project XRAY. When I think about Open Source, the first that comes to my mind is GNU/Linux. This operating system was developed by Linus Torvalds and Richard Stallman in the early 90’s, then all the code was released to the community. Now, this first operating system has grown, and we can
  10. How to find documentation about DSP and FPGA. Sometimes I receive emails or direct messages on LinkedIn from readers asking me about where they can find documentation about DSP, FPGA or both together. Unfortunately, I did’t find webpages where talk about how to make dsp on an FPGA, but there are a s
  11. True RMS compute in FPGA. When we are designing an acquisition system, sometimes process the signal is not enough, there are many cases where the project requires that the value of a measurement must be shown in a user interface. This is very easy when we are working with DC signals, since we can se
  12. Adding the Digilent USB104 A7 board to Litex. In this blog we already talk about Litex in this post, and also we used Litex to run Linux in a SoC in this post. If we remember the flow, the steps are very simple. We need to execute some Python scripts in order to generate the HDL code. Then, that HDL
  13. How to use a digital oscilloscope. When we is studying a degree related with electricity (electronics, electronics, electrical, communications, …), one of the elements which is very familiar to us is the oscilloscope. I remember when I started my electronics course (here in Spain we call it professi
  14. Division algorithms in FPGA. Digital signal processing involves many different operations. Although there are some algorithms with a high level of digitalization, they can be computed only with additions and shifts, others require specific hardware. For example, we need multiplicators to use an IIR
  15. Frequency warping using the bilinear transform. The process to design a IIR filter is always the same. First of all we have to design the design the filter using its continuous transfer function, then, once the natural frequency of the filter, the order and the quality factor are selected, we will o
  16. Exploring the Cordic algorithm. Many years ago, the processors were slow, and they only can compute additions and, spending some time, multiplications. Calculating division was a hard task, and no mention trigonometric operations and square roots. As low resources makes the people smarter, in 1959,
  17. FilterBuilder v0.1 As I said in other posts, I am FPGA designer in a company. My functions are, between others, implement the signal acquisition and apply different digital signal processing algorithms, to obtain a signal that the FPGA can use to control the power electronic device. My regular workf
  18. Running Linux on a Litex SoC. That FPGA are very versatile devices is something that everybody knows, and the fact that you can implement inside many different processors makes the FPGA very interesting devices for test different processors architectures. In this blog we already saw the benefits of
  19. Proportional – Integral regulator. Implementation and verification. In the last post we talked about digital control loops. In short, we talked about the elements that we can find in digital, or analog, control loops. The first of them is an element to acquire the difference between the actual outpu
  20. Digital control loops. Theoretical approach. In this blog, I have tried to show you different tools, usually in the field of digital signal processing, so you can select the correct tools for your projects. This time we will use the tools that we have used in other posts but for a different purpose,
  21. Downsampling using MATLAB and the Microchip's Icicle kit. Many times we need to manage low-frequency signals sampled at high rates. This can be due to the need to detect edges in that signal as fast as possible, for example, if we are using that signal to protect a device. This kind of situation mak
  22. Running Petalinux on a Microblaze soft core. You can do everything with an FPGA. I have used this sentence many times in my job, and most of them followed by, its all a time matter. Also, in this blog I have said many times that FPGA are very adaptable devices, and they fit in many projects. In addi
  23. Designing a FM receiver with the USRP B205mini #WorldRadioDay22. While we are driving on the way to our jobs, we have the 99.9% of our attention on the road, but I am sure that the other 0.1% of our attention is focused on the radio. Radio has been with us for most than 100 years, and today is its d
  24. Ripple suppression circuit for PWM DAC. If we are working with analog signals, is very common that we will need an analog level for set an offset if we are working with a bipolar signal, or maybe we will need an analog level to set a threshold. In these cases, the theory says that we will need a dig
  25. Building a SoC with Litex. There are many cases where we will need a processor inside our FPGA. In my case, soft cores are very useful when I have to implement in the FPGA a manager for an external device using high level interfaces like ethernet or modbus. For this interfaces we can find in the int
  26. Why FPGA? This will be the first post of 2022, and I want it to be different. Time ago I have been thinking to write about how I started to use FPGA and also what I expect of them for the future. Likely, the thoughts that I am going to write in this post will change in the next year, but it would be

2021 25

  1. Getting started with Microchip’s FPGA Icicle Kit and PolarFire SoC. In these rare days when getting a development board with a new FPGA is increasingly difficult, a new board has come into my hands. The board is the Icicle Kit, a Single Board Computer (SBC) from Microchip Technology. It is based on
  2. Discovering Gowin FPGA. A few weeks ago Dialog Semiconductor announced a new series of FPGAs named ForgeFPGA. The highlight of these new devices are not high processing power, the highest speed or the big they are, the main highlights of these devices are Low-Power and Low-Cost. This kind of announc
  3. Single pole filter without multiplications. When I am working in a design for an FPGA, which involves the acquisition of any signal, I usually have to design a filter before using that signal in the control loop, or a protection. If the use of this signal is critical, like the mentioned before, I us
  4. Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7 If I say “software for engineering”, most of you probably think of MATLAB. I don’t know if there is any field in engineering which does not have a package in MATLAB, and digital signal processing and FPGA design are
  5. Remote debugging via hardware server. In my daily life, as with other FPGA developers, I have a laptop where I write the code, and I connect to a remote host to synthesize and implement the FPGA designs. This offers me many advantages. The most important one is that I don’t need a very powerful proc
  6. Implementing high order filters with FIR Compiler. Many times, in our designs we find a signal that our interest band of frequency is very close to the band that we need to reject. In this case, in general, the most efficient way to attenuate the unwanted signal is using a 4th or 6th order IIR filte
  7. FFT algorithm using an FPGA and XDMA. In this blog we talked (a little) about the xDMA IP from Xilinx, and how to send and receive data through PCI using an FPGA. On that occasion, we used the Picozed board with the FMC Carrier gen 2. This time the board used Litefury from RHS research. This board i
  8. Controlling a SMPS from MSS with SmartFusion2 SoC. FPGAs have been present in the telecommunications field for many years, almost since they were created. On the other side, there are fields where FPGAs have not arrived yet for several reasons such as power consumption or price. But there are other
  9. Implementing a dual core processor in FPGA. A few years ago, microprocessors manufacturers competed to get the fastest processor. High speed means more tasks can be executed in the same amount of time, but also, means higher power consumption. To improve this, the voltages of the core start decreasi
  10. Using PCIe in Xilinx 7 Series. When we look into communicating an FPGA with a computer, the first interface that we can find is UART, but this interface has several limitations in terms of speed. In order to transfer a high amount of data between the CPU and an FPGA, we will need to use some more so
  11. Creating Pynq images for custom boards. In this blog we already talk about Pynq and how it can help us to develop some applications in a easy way. Obviously, Pynq has its limitations but it is still a powerful tool with which we can develop projects in a few minutes. Pynq is Jupyter-notebook based,
  12. Equalizing IIR filters for a constant group delay. In the previous post, I designed an audio equalizer. In that design, I used 3 different FIR filters to split 3 different frequency bands in order to send them to different speakers. Very low frequencies will be sent to the sub-woofer, medium frequen
  13. Audio equalizer based on FIR filters. Digital signal processing can be used in almost all engineering fields, from seismology, to obtain the distance where an earthquake has been generated, to data science, but these areas use digital signal processing as a way to obtain real interest data. On the o
  14. Creating a RISC-V based design on SmartFusion®2 SoC. Everybody knows that the processor of the moment is the RISC-V, even it is not a processor itself, the amount of the boards based on RISC-V is growing more and more. To understand the reason of that, we have to understand what is RISC-V, and what
  15. Adding windows to xFFT IP. Digital signal processing algorithms are, in general, purely mathematical algorithms that works perfectly on our notebook or MATLAB, but in real design, the algorithm starts to return us some unexpected results. One example of that is the quantification error. While in MAT
  16. Implementing a FIR filter using folding. In this blog we have seen how to develop an FIR filter. In this post you have an example of FIR filter where the coefficients are configured through AXI4-Lite interface. The goal of that post was the implementation of a configurable digital signal processing
  17. Discovering the SmartFusion® 2 SoC. Several years ago, electronic designs began to feature System on a Chip (SoC) technology. This technology is an excellent choice for designs that require a higher integration or a reduction in Bill of Materials (BOM) cost. On this blog we have seen how, by combini
  18. Implementing a digital biquad filter in Verilog. Filtering is likely the most common DSP algorithm that any embedded engineer has to design, no matter if they are developing for an STM32, TI DSP or, of course, an FPGA. Filtering is important because the majority of the applications are connected to
  19. Managing AXI4-Stream from MATLAB. For developers who work with FPGA and digital signal processing, and for signal processing, I mean audio signals, video signals, and radio signals, … sure they have used the AXI4-Stream protocol. The AXI4-Stream protocol is used as a standard interface to connect co
  20. Development boards I use. Many times, developers who want to take their first steps in the world of FPGAs to ask me about a development board that begins to test their first designs. From the newie point of view, I understand that seeing a led blinking can be very satisfying, but from my point of vi
  21. Using IIO to manage an ADC from Petalinux. Managing an ADC is something that any engineer dedicated to signal processing has to do very often. This task, in general, use to be no much complicated, unless you are using a high-speed ADC with LVDS interface or something similar, but that kind of ADCs a
  22. Connecting an SSD to Zynq MPSOC. Devices like Xilinx Zynq or Microchip PolarFire give us the possibility to mix in a single design a high-level OS like Linux and a fast device like FPGA. For signal processing, or even data science, is very interesting to acquire an event at rates of several tens of
  23. Using HDL Coder WFA to implement a distortion effect. If you have read some posts on this blog, you can see that FPGAs are a very good choice if you want to develop some digital signal processing algorithm, but for some reason, maybe because they are (a bit) more complex than DSP, FPGAs they are not
  24. Using FPGA Data Capture to debug a design. In the project developed in this post, to verify the behavior of the filter, we used the data acquired from the ILA. Data were processed on MATLAB with a script where we read the CSV, and verify input and output signals. This process works, but MATLAB gives
  25. Using DSP48E1 Slice. A few years ago, FPGAs were used almost exclusively for communication systems. On the other hand, DSPs are used to execute digital signal processing algorithms. The reason is the hardware components that were integrated. FPGAs, were based on flip-flops, LUTs and general logic, u

2020 20

  1. Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2) In the last post, we had designed a filter with filter designer tool from MATLAB. After verifying the filter on MATLAB and Simulink, we have to generate the HDL and verify the implementation using FPGA-in-the-Loop, and later, verify the f
  2. Using MATLAB and FPGA-in-the-Loop to design a filter (Part 1) If I say “a software for engineering”, most of you probably think on MATLAB. I don’t know if exist any engineering field which have not a package on MATLAB, and obviously, digital signal processing and FPGA design is not one of them. The
  3. Discovering SDR with GNU Radio and USRP B205Mini. This post will be different from what I usually write. In general, in my posts, I talk about low-level algorithms and FPGA implementations to do digital signal processing, but this time I will use software to configure an specific purpose board. The
  4. Increasing ADC resolution using oversampling. After a few post dedicated exclusively to the FPGA, on this post I going to talk about a technique that can help us to improve the ADC resolution. To study this technique, we will use as a example the ADC which is based the Digilent’s ZMOD ADC, the AD964
  5. Using Xilinx’s FIR Compiler. When we need a FIR filter, in general, or at least in my case, we already have a FIR filter HDL, where we only need to change the filter order to the application needs, in most cases this configuration can be parametrized, and the second thing we have to do is compute, q
  6. Creating an AXI Stream IP for an acquisition system. On the last post, we talk about the using of DMA to send data between PL and PS on SOC or MPSOC devices. The example that I proposed, was a kind of FFT compute accelerator, where a signal stored on the DDR was sent to the PL, and here, an FFT was
  7. Using the DMA and AXI4 Stream on Zynq US+. When we are working with a SOC or MPSOC, is very common the data interchange between the PL and the APU, or between the PL and the RPU. To do that, the Zynq platform gives us several interfaces between the PL and both APU and RPU aka PS. In case of Zynq MPS
  8. Designing an FPGA board. Few month ago, I decided to design my own FPGA development board. The main reason for that was simply learn to do it, because I have design a lot o boards for peripherals, PMODs, or other projects, but never one based on FPGA, and for me, route a BGA was a big challenge.
  9. Asymmetric multiprocessing on Zynq MPSOC. On many applications, specially when we talk about signal processing, on the same application there is a mix of real time processing and a non-real time operating system, or on machine learning applications, when we can have a mix of a fast acquisition syste
  10. Using moving average filters for hard filtering. It’s September, most of you will come back to work, others don’t remember what is that of holidays, and others, luckiest people, will start your holidays soon. I am in the first group, so I have to back to work, and also, back to write here :).
  11. Custom AXI IP for acceleration. I will use this post to show you how, creating an AXI IP, we can accelerate our applications on Petalinux, or in case we use a Zynq MPSOC, we also can accelerate an application running in the RPU.
  12. Single tone detector with Genesys ZU and RTU. When I started to investigate about signal processing, what made me feel happier was decode a signal that, apparently, has no sense. Discrete Fourier Transform (DFT) turns something meaningless into something meaningful. That is amazing but, if we are lo
  13. Genesys ZU and Zynq US+. This week I have received the big (big) sister of the Eclypse Z7, the Digilent’s Genesys ZU. This board, due to its FMC, ZMOD and PMOD is a good choice for digital signal processing applications, but first, let’s take a look to its brain, a powerful Zynq Ultrascale +.
  14. EclypseZ7, Petalinux and signal processing at the edge. In my last post, I said 2 things come to my mind when we talk about signal processing. One of them is FFT, and I explained you how to compute an xFFT on the Digilent’s EclypseZ7, or other Xilinx 7 series device, the other thing that I talked, w
  15. Eclypse Z7 and xFFT. When we talk about digital signal processing, 2 things come to my mind. First one is the sinc wave, used as a cover page of a lot of books about signal processing, and the second one, is the fourier transform.
  16. Eclypse Z7, ZMODs and SYZYGY. Few months ago, Digilent presented their new development platforms based in Zynq and Zynq US+, with connectors compatibles with SYZYGY standard. This standard is in the middle between PMOD and FMC, with the enormous advantage that can be soldered by makers, with a solde
  17. Emulating hardware with Zynq. Due to quarantine, most of us are working from home, and seems that the way we used to work, even more when our work consist in write or develop with our laptop, will be change. When your work is computer based, for example, on web, is easy still working from home with
  18. Real time filter compute with PYNQ We are in front of our customers, we have our design fully tested in our lab, all analog and digital filters works perfectly, but, in the customer installations there are an unknonw noise source. In this case, we must recompute digital filters, and spend time re si
  19. DDR Resources When most of us hear DDR, the first think that comes to our mind is RAM memories, but DDR is related with the comunication protocol, not with the memory. DDR means Double (Dual), Data Rate. This, basically means that un 1 single clock cycle, 2 data will be sended for every line. In thi
  20. Why I use scripting? When I started with FPGA, like probably all of us, the first thing I did when I arrived at my job position was to start Vivado (or ISE), and start coding, and once the code was write, cross my fingers, and Generate Bitsream. If all works fine, after some minutes (or hours), we h