The Curious Engineer

All blogs / Embedded / microcontrollers

Daniel Mangum

danielmangum.com/posts

Daniel Mangum's personal website

Embedded / microcontrollersCPU / microarchitectureFPGA / HDLElectronicsAI / ML

’18’19’20’21’22’23’24’25’26
Posts
106 from 21 Jun 2018 to 21 Oct 2026
Posting
monthly (16 in the last year)
Kind
personal blog
Feed
https://danielmangum.com/posts/index.xml

2026 12

  1. Your MCU Likely Escaped the eMudhra Intermediate CA Compromise
  2. What's on that Access Port?
  3. When the Debugger Lies
  4. Farewell Golioth... and Hello Nordic!
  5. The Simple Elegance of the Integrated Timing Belt Loopback Fastener
  6. Leadership Lessons from The Odyssey
  7. JLink JTAG Access on the Pinecil
  8. Floating Point Fun on Cortex-M Processors
  9. PSA Crypto: The P is for Portability
  10. Fooling Go's X.509 Certificate Verification
  11. Making Ferrite Core Inductors at Home
  12. 3,500 Miles in 2025

2025 10

  1. Fixing My System76 Laptop in 20 Minutes or Less
  2. Determining Current Arm Cortex-M Security State with GDB
  3. Make it Possible, Then Make it Normal
  4. Interesting SPI Routing with iCE40 FPGAs
  5. Using a Laptop as an HDMI Monitor for an SBC
  6. How AI on Microcontrollers Actually Works: Registering Operators
  7. How AI on Microcontrollers Actually Works: The Computation Graph
  8. How AI on Microcontrollers Actually Works: Operators and Kernels
  9. Just Barely Fitting a Full Wi-Fi Stack on the nRF9151
  10. Accessing the Qualcomm Modem over USB on the RAK5010

2024 14

  1. VPR: Arm and RISC-V Inter-Processor Communication
  2. VPR: Nordic's First RISC-V Processor
  3. USB UART on the Thingy:91 X
  4. This Website is Hosted on Bluesky
  5. USB On-The-Go on the ESP32-S3
  6. Is It Better to Fail Spectacularly?
  7. The Taxonomy of Hardware Security Mechanisms
  8. Founder Mode for Non-Founders
  9. Static Allocation in External RAM on ESP32
  10. Wireframes are Cheap, Engineering Should Be Too
  11. The Most Important Skill in Startup Engineering Leadership
  12. RISC-V Bytes: Accessing the Pinecil UART with picoprobe
  13. RISC-V Bytes: Soldering the Pinecil Breakout Board
  14. Reflections on Running 3,000 Miles in 2023

2023 26

  1. Understanding Every Byte in a WASM Module
  2. Zero to WASI with Clang 17
  3. Supercon 2023 Day 3: badgecase.io
  4. Supercon 2023 Day 2: Talks Begin, Hacking Continues
  5. Supercon 2023 Day 1: Hello Badge
  6. Setting Up Verible for Verilog with Neovim
  7. A Particularly Gnarly Case of Go’s Non-Nil Interfaces
  8. How LUTs Are Used as Storage Elements on an FPGA
  9. The Value of Livestreaming Long-Term Projects
  10. When Does Vivado Infer BRAM?
  11. Microprocessors Are Tiny, But They Can’t Fit in Your Head
  12. A Brief Retrospective on SPARC Register Windows
  13. How To Dissect a Critical HackerNews Comment
  14. A Single-Cycle 64-Bit RISC-V Register File
  15. Single-Cycle and Multicycle Do Not Describe Processor Performance
  16. Why Create a New Instruction Set Architecture?
  17. A Three Year Bet on Chip Design
  18. RISC-V Bytes: Semihosting with Zephyr on an ESP32
  19. RISC-V Bytes: Zephyr Before Main
  20. RISC-V Bytes: Zephyr on the ESP32
  21. RISC-V Bytes: Exploring a Custom ESP32 Bootloader
  22. Do you want to take a leap of faith?
  23. Where does the kubelet mount volumes?
  24. K8s ASA: Watching and Caching
  25. K8s ASA: The Storage Interface
  26. Welcome to Kubernetes API Server Adventures

2022 8

  1. RISC-V Bytes: Timer Interrupts
  2. I'm on Mastodon
  3. RISC-V Bytes: Go 1.19's Register-Based Calling Convention
  4. RISC-V Bytes: Stack Use After Return in C, Go, and Rust
  5. Sandbox Programmers
  6. Graceful Shutdown of Responsibilities in a Growing Organization
  7. The Missing Kubernetes Type System
  8. RISC-V Bytes: Rust Cross-Compilation

2021 14

  1. RISC-V Bytes: Privilege Levels
  2. How Kubernetes Validates Custom Resources
  3. Infrastructure in Your Software Packages
  4. RISC-V Bytes: Introduction to Instruction Formats
  5. Announcing the Research Triangle RISC-V Community Group
  6. RISC-V Bytes: Passing on the Stack
  7. Stepping Away from Upstream Kubernetes
  8. RISC-V Bytes: Caller and Callee Saved Registers
  9. RISC-V Bytes: Cross-Platform Debugging with QEMU and GDB
  10. Using a ConfigMap as an OCI Image Cache
  11. chdir to cwd: permission denied
  12. Is Crossplane the Infrastructure LLVM?
  13. Scraping controller-runtime Prometheus Metrics Locally
  14. Rate Limiting in controller-runtime and client-go

2020 10

  1. Conference Talk: Building an Enterprise Infrastructure Control Plane on Kubernetes
  2. Installing Vivado 2020.x on Ubuntu 20.04
  3. Tweet Thread: Crossplane Packages and K8s Features You Thought You Didn't Have
  4. Understanding Non-Local Jumps (setjmp/longjmp) in RISC-V Assembly
  5. Podcast Guest: Using Kubernetes And Crossplane To Provision Cloud Infrastructure (Full Stack Journey)
  6. Uppercase .S vs Lowercase .s File Extensions in GAS Syntax Assembly
  7. Podcast Guest: What is Rapid Prototyping? (The DroidDevCast)
  8. Podcast Guest: Daniel Mangum on Crossplane, building a PaaS, and Multi-Cluster Kubernetes (LOTE)
  9. Guest Post: Adding Managed Services to Serverless with Crossplane and OpenFaaS (OpenFaaS Blog)
  10. Guest Post: Connecting AWS managed services to your Argo CD pipeline with open source Crossplane (AWS Open Source Blog)

2019 8

  1. Podcast Guest: Gerhard goes to KubeCon (part 2) (The Changelog)
  2. Please Mind Your Metaphors
  3. HashiCode Ep. 1: Terraform Remote State Backend Locking
  4. Introducing HashiCode
  5. Presence vs. Planning
  6. Understanding ETL to ELT by Going to Costco
  7. Immediate Reflections on the AWS Solutions Architect Associate Exam (February 2019)
  8. Why You Shouldn't Use ^Parameters with CloudFormation Templates

2018 4

  1. Dockerfile for Building Ionic Apps
  2. Simple Linux Command Line Using Docker
  3. Local Kong API Gateway for Go Web Server
  4. Why I am Starting a Blog