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Domipheus Labs

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FPGA / HDLCPU / microarchitectureGame development

’15’20’25
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59 from 1 Mar 2012 to 29 Jun 2025
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now and then
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2025 1

  1. Why FPS matters when comparing upscaling quality

2024 1

  1. Colin Riley: Life Log

2022 1

  1. Designing a RISC-V CPU in VHDL, Part 22: Doom as a benchmark and adding Cache to RPU

2021 2

  1. Writing the SPI flash of the miniSpartan3 FPGA board
  2. Designing a RISC-V CPU in VHDL, Part 21: Multi-cycle execute for multiply and divide

2020 2

  1. Designing a RISC-V CPU in VHDL, Part 20: Interrupts and Exceptions
  2. Designing a RISC-V CPU in VHDL, Part 19: Adding Trace Dump Functionality

2019 5

  1. Raspberry Pi 4 PCI Express: It actually works! USB3, SATA… GPUs?
  2. Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit
  3. Designing a CPU in VHDL Series Quick Links
  4. Privacy Policy
  5. Flashback: Quake 3/RTCW Level Design

2018 4

  1. Designing a RISC-V CPU in VHDL, Part 17: DDR3 Memory Controller, Clock domain crossing
  2. Designing a RISC-V CPU in VHDL, Part 16: Arty S7 RPU SoC, Block Rams, 720p HDMI
  3. Designing a CPU in VHDL, Part 15: Introducing RPU
  4. HDMI over Pmod using the Arty Spartan 7 FPGA board

2017 1

  1. The Boat PC – a marine based Raspberry Pi project

2016 8

  1. Porting my VHDL Character Generator to Spartan3: Reducing clock speeds and pipelining
  2. Designing a CPU in VHDL, Part 14: ISA changes, software interrupts and bugfixing that BIOS code
  3. Getting Started with the miniSpartan3 FPGA board
  4. Designing a CPU in VHDL, Part 13: Memory system and BIOS beginnings
  5. Designing a CPU in VHDL, Part 12: Text mode video output
  6. Designing a CPU in VHDL, Part 11: VRAM and HDMI output
  7. Dear ImGui, Thanks, From TEMU – The TPU Emulator
  8. Designing a CPU in VHDL, Part 10b: A very irritating issue, resolved.

2015 17

  1. Designing a CPU in VHDL, Part 10: Interrupts and Xilinx block RAMs
  2. Designing a CPU in VHDL, Part 9: Byte addressing, memory subsystem and UART
  3. A UART Implementation in VHDL
  4. Designing a CPU in VHDL, Part 8: Revisiting the ISA, function calling, assembler
  5. Designing a CPU in VHDL, Part 7: Memory Operations, Running on FPGA
  6. Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
  7. Designing a CPU in VHDL, Part 5: Pipeline and Control Unit
  8. Designing a CPU in VHDL, Part 4: The ALU, Comparisons and Branching
  9. Designing a CPU in VHDL, Part 3: Instruction Set Architecture, Decoder, RAM
  10. Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, register file, testing
  11. Designing a CPU in VHDL, Part 1: Rationale, tools, method
  12. Teensy Z80 Homebrew Computer – Part 6 – Asynchronous Clocking Fail
  13. Teensy Z80 Homebrew Computer – Part 5 – Implementing preemptive multithreading
  14. Teensy Z80 – Part 4 – VRAM explained, display modes, simple shell.
  15. Teensy Z80 – Part 3 – File System, SD Card, VRAM?
  16. Teensy Z80 – Part 2 – Mode 2 Interrupts, Timer
  17. Teensy Z80 – Part 1 – Intro, Memory, Serial I/O and Display

2014 11

  1. KiCad – Adding bridges / links to single sided PCB layouts
  2. Pi On The Wall – wall mounted home server – Part 4: Putting it together
  3. Video: PiOnTheWall – Wall Mounted Touchscreen Raspberry Pi Home Server
  4. Video: Windows Developer Program for IoT – Galileo Development Kit Unboxing.
  5. Pi On The Wall – wall mounted home server – Part 3: Reducing Power Consumption
  6. Pi On The Wall – wall mounted home server – Part 2: Diet Pi
  7. Pi On The Wall – wall mounted home server – Part 1: Introduction
  8. Cheap 1.8″ SPI 128×160 TFT Module – Arduino wiring!
  9. Project BoilerLog: SD Datalogger with RTC
  10. Electronics
  11. A change

2012 6

  1. Gears of Glory: Apex Ace – Singleplayer Game Modes
  2. Gears of Glory: Apex Ace Pricing
  3. Lessons from exhibiting at an Indie Festival
  4. Gears of Glory: Apex Ace status update
  5. Press Release: Gears of Glory: Apex Ace announced.
  6. Leaderboard Ordering