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Tales on the wire

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FPGA / HDL Electronics Networking

’23 ’24 ’25 ’26

Posts: 28 from 29 Jul 2023 to 16 Sep 2026
Posting: monthly (17 in the last year)
Kind: personal blog
Feed: https://essenceia.github.io/index.xml

2026 15

16 SepWorst Is Better
23 JulDesigning an Ethernet Switch ASIC
23 JulShow More
20 JulFCC has sudo rights: new regulation on consumer grade routers.
4 JulUntil Heat Death Do Us Part
29 JunThe door out of Tapeout Hell
29 MayExceptional engineers
12 MayThe hardware isn't broken, the documentation is !
4 AprUgly by Design
3 AprFloating point from scratch: Hard Mode
29 MarTentpole Projects
25 FebAlibaba cloud FPGA: the 200$ Kintex UltraScale+ [Updated]
7 FebTextures of growing up
20 JanWhy wait for the AI bubble to pop to tapeout AI accelerators?
2 JanTwo weeks until tapeout

2025 2

30 DecBLAKE2s Hashing Accelerator: A Solo Tapeout Journey
16 DecReflexion on mortality

2024 1

21 JanTroubleshooting the redstone D2020, part 2

2023 10

13 NovMoldUDP64 and ITCH testbench
1 NovITCH RTL implementation
9 OctCustom STM32H750 embedded development board
2 OctEthernet 10GBASE-R and 40GBASE-R PCS
2 OctTroubleshooting the redstone D2020
2 AugHardware Gallery
2 AugHi, I'm Julia
2 AugMoldUDP64 RTL implementation
30 JulAES 128b RTL implementation
29 JulBLAKE2 RTL implementation