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What are you optimizing for?
Computer Architecture, Computer Arithmetic, RISC-V. Click to read "What are you optimizing for?", by FPRox, a Substack publication with hundreds of subscribers.
CPU / microarchitectureMathSecurityAssemblyPerformance / optimization
- Posts
- 68 from 3 Aug 2016 to 11 Oct 2026
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- monthly (9 in the last year)
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2026 8
- RISC-V Bulk Normalization Algorithm (RVBNA)
- Is Some Lattice-Based Post-Quantum Cryptography Broken? (update: No!)
- RISC-V's Zvzip is Changing
- Manifest for RISC-V Constant Time Floating-Point Operations
- RISC-V and Floating-Point
- Emulating future RISC-V Vector extensions
- RISC-V Vector Is Expanding
- RISC-V and Post Quantum Cryptography
2025 8
2024 8
- Quick Note: swapping pairs with RVV
- Number Theoretic Transform with RVV
- Accelerating CRC with RISC-V Vector
- Unpacking the CanMV K230 RISC-V board
- RISC-V Scalar Bit Manipulation Extensions
- Partial Taxonomy of 8-bit Floating-Point Formats
- Implementing Softmax using RISC-V Vector
- Transposing a Matrix using RISC-V Vector
2023 19
- RVV implementation of Keccak / SHA-3 (part 1)
- RISC-V Vector Programming in C with Intrinsics
- Zimop/Zcmop may-be-operations
- RISC-V support for BFloat16
- RISC-V Smcntrpmf: mode filtering for Zicntr
- RVB profile: application class profile with options
- RISC-V vector crypto spec freeze update
- Zfa: even more floating-point operations
- Adding a new RISC-V instruction (to LLVM)
- Zicond: RISC-V integer conditional operations
- Adding a new RISC-V instruction (to spike)
- RISC-V Profiles
- Sneak peek at RISC-V RVA23(U64) profile
- RISC-V Vector Cryptography Extension (2/2)
- RISC-V Vector Cryptography Extensions (1/2)
- RISC-V Vector in a Nutshell
- RISC-V Vector extension in a nutshell (part 1)
- RISC-V Vector Element Groups
- RISC-V Compressed Instructions (part 2): Zc extensions
2022 12
- RISC-V Compressed Instructions (part 1): C extension
- RISC-V Vector Register Groups
- How to read a RISC-V Vector assembly instruction
- Support of half precision floating-point format in RISC-V ISA: Zfh(min), Zvfh(min)
- RISC-V Register Files
- RISC-V Vector extension in a nutshell (Part 5.2): vector loads and store
- RISC-V Vector extension in a nutshell (Part 5.1): vector loads and store
- RISC-V Vector Extension in a Nutshell (Part 4): permute operations
- RISC-V Vector Extension in a Nutshell (Part 3): mask & masked operations
- RISC-V Vector Extension in a Nutshell (Part 2): arithmetic operations
- New option for RISC-V Vector performance simulation
- Performance simulation of RISC-V vector extension using GEM5