The Curious Engineer

All blogs / Compilers

Wickopedia

johnwickerson.wordpress.com

A blog by John Wickerson

CompilersFPGA / HDLCPU / microarchitectureMath

’10’15’20’25
Posts
75 from 22 Jan 2009 to 26 Sep 2026
Posting
now and then (4 in the last year)
Kind
personal blog
Feed
https://johnwickerson.wordpress.com/feed/

2026 3

  1. In which John becomes a Machine Learning researcher!
  2. How do bitwidths actually work in Verilog?
  3. Finding bugs in FPGA place-and-route tools

2025 1

  1. Are conference reviewers harsher when they have a submission of their own?

2024 10

  1. Fuzzing Quantum Compilers
  2. The Hoare Cube
  3. Fun with income tax
  4. Who checks the equivalence checkers?
  5. Automated feature testing of Verilog parsers using fuzzing
  6. In praise of Freddy, My Love
  7. Mix-testing: revealing a new class of compiler bugs
  8. Cycling from King’s Cross to Imperial College London
  9. Verified high-level synthesis – now with hyperblocks!
  10. What is the other Incorrectness logic?

2023 3

  1. CXL: What’s all the fuss about?
  2. The fastest route between King’s Cross St Pancras and South Kensington
  3. Hyphenation: when and why?

2022 4

  1. Proving the existence of God using a computer
  2. “A Squash and a Squeeze” – Academic Edition
  3. Some reflections on FCCM 2022
  4. The “Cluedo” effect in randomised testing

2021 5

  1. High-level synthesis, but correct
  2. What’s the Rush?
  3. Understanding the memory semantics of multi-threaded CPU/FPGA programs
  4. Introducing C4: the C Compiler Concurrency Checker
  5. Fuzzing High-Level Synthesis Tools

2020 5

  1. A translation puzzle
  2. Diagrams for Composing Compilers
  3. Uncovering multicore interference
  4. Highlights from FPGA 2020
  5. New names for odd and even functions

2019 7

  1. Fuzzing FPGA synthesis tools
  2. A plot twist! Drawing better graphs in PL papers
  3. In praise of scatter plots
  4. Loop invariants – where should we put them?
  5. Modulo scheduling with rational initiation intervals
  6. How to draw block diagrams
  7. A wordless proof

2018 7

  1. A rant about fire doors
  2. Never Say Never Again – chords
  3. Greatest hits of PLDI 2018
  4. What is the difference between latency and throughput?
  5. Greatest Hits of FCCM 2018
  6. Concurrency-aware scheduling for high-level synthesis
  7. What do you get if you cross Weak Memory with Transactional Memory?

2017 4

  1. Who has the most POPL and PLDI papers?
  2. So, who has the most FPGA, FCCM, FPL, and FPT papers?
  3. Ribbon Diagrams for Weak Memory
  4. Translating lock-free, relaxed concurrency from software into hardware

2016 5

  1. Memory Consistency Models, and how to compare them automatically
  2. cppreference.com gets acquire/release instructions wrong
  3. Why we should plot normalised data on a logarithmic scale
  4. Bad UX design: “Updated Just Now”
  5. Aqua Marina – piano sheet music

2015 2

  1. Tips for commuting between Cambridge and London
  2. On the letter O and the number 0

2013 2

  1. Some useful and free Mac apps
  2. The Isabelle logo as end-of-proof symbol

2012 1

  1. Why apostrophes are important…

2011 4

  1. Trivia+cryptic crossword
  2. How to fix a Roland HP 136 Digital Piano
  3. Adding PDFs to BibDesk
  4. Chrome-style tabs for…

2010 5

  1. A star operator for functions
  2. A comment on ‘Abstract Separation Logic’
  3. Installing LaTeX fonts on Mac OS X
  4. MathUnicode keyboard layout
  5. A little theorem about odd powers

2009 7

  1. Partial and total correctness as greatest and least fixpoints
  2. A new wifi logo
  3. “Concurrent Buns” – A chef’s guide to concurrency verification
  4. A proof environment for LaTeX
  5. A new notation for building sets?
  6. Does lub-preservation imply monotonicity?
  7. Implementing Difference Lists in Prolog