The Curious Engineer

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systemverilog.io

systemverilog.io

A site made for SoC Architects, RTL Designers, DV, Emulation and Validation Engineers, that condenses decades of SoC/ASIC development experience into easy to understand tutorials with tons of code examples

FPGA / HDLCPU / microarchitecturePython

’15’20’25
Posts
45 from 8 Apr 2013 to 4 Oct 2024
Posting
quiet since 2024
Kind
personal blog

2024 2

  1. Chapter 1 - Python lists and dictionaries - systemverilog.io
  2. Chapter 0 - Setting up Python - systemverilog.io

2013 1

  1. HP Moonshot Dissection - systemverilog.io

Undated 42

  1. Almost finished - systemverilog.io
  2. Thank you for signing up to the SVIO Newsletter - systemverilog.io
  3. ASIC/SoC Design - systemverilog.io
  4. DDR4 Tutorial - Understanding the Basics - systemverilog.io
  5. DDR4 SDRAM - Initialization, Training and Calibration - systemverilog.io
  6. DDR4 SDRAM - Timing Parameters Cheat Sheet - systemverilog.io
  7. Facebook and the Open Compute Project - systemverilog.io
  8. LPDDR5 Tutorial - Deep dive into its physical structure - systemverilog.io
  9. Modular Design in Open Compute Project - systemverilog.io
  10. DDR4 SDRAM - Understanding Timing Parameters - systemverilog.io
  11. Engineering - systemverilog.io
  12. How to conduct a technical interview - systemverilog.io
  13. systemverilog.io Newsletter - systemverilog.io
  14. Python for ASIC/SoC Engineers - systemverilog.io
  15. Chapter 2 - Python numbers - systemverilog.io
  16. Chapter 3 - Python Print Formatting - systemverilog.io
  17. Chapter 3 - Python strings - systemverilog.io
  18. Highlight.js CDN Assets - systemverilog.io
  19. DIGESTS - systemverilog.io
  20. ASIC, FPGA, SoC Verification - systemverilog.io
  21. A Blueprint for Formal Verification - systemverilog.io
  22. SystemVerilog Constraints Examples - systemverilog.io
  23. SystemVerilog Enum - systemverilog.io
  24. SystemVerilog Generate Construct - systemverilog.io
  25. A Gentle Introduction to Formal Verification - systemverilog.io
  26. Lrm - systemverilog.io
  27. SystemVerilog Macros - systemverilog.io
  28. SystemVerilog Random Stability - systemverilog.io
  29. SystemVerilog Randomization & Random Number Generation - systemverilog.io
  30. Splitting and extracting specific modules from VPD or VCD dump - systemverilog.io
  31. SystemVerilog Style Guide - systemverilog.io
  32. SystemVerilog Assertions Basics - systemverilog.io
  33. SystemVerilog Associative Arrays - systemverilog.io
  34. SystemVerilog Casting - systemverilog.io
  35. SystemVerilog convert hex, int, binary data type to string - systemverilog.io
  36. SystemVerilog convert string to hex, int, binary data type - systemverilog.io
  37. SystemVerilog Dynamic Arrays - systemverilog.io
  38. SystemVerilog Queues - systemverilog.io
  39. Methods and utilities to manipulate SystemVerilog strings - systemverilog.io
  40. 10 SystemVerilog Utilities You Must Know - systemverilog.io
  41. UVM field macros - systemverilog.io
  42. How to Create & Use VMC (SWIFT) Models - systemverilog.io